The present invention is directed to electronic circuits and, more particularly, to a processor that is switchable between a test mode and a debug mode of operation, in addition to a functional mode of operation.
Development of a new processor or of an evolution of an existing processor requires testing of the combinational logic of the circuits of the processor in a test mode, and debugging of programs installed in the processor in a debug mode. Testing is commonly performed by automatic test equipment (ATE) having a test controller unit (TCU) through a TCU test access port (TAP) of the processor. Debugging is performed through a debug access port (DAP) TAP. The DAP TAP also may be used for programming or re-programming software in the processor.
Testing of the processor at the fab is typically performed on the wafer, the test machine connecting with individual devices in the array of bare dies on the wafer through probes contacting pads on the devices. After packaging, the devices are typically tested again, in ‘final test’, the test machine connecting with the devices through external contacts (pins) on the package, to check the impact of the packaging on performance and to diagnose any packaging related defects such as faulty connections and other defects that can only be tested on packaged parts. The TCU TAP includes physical internal connections, logic elements and software to enable the test machine to apply test signals or instructions to the device placing the modules of the device in specific test configurations and putting the device through specific test routines instead of its normal functional operation. To facilitate the testing, the devices may include boundary scan resources, and/or built-in self test (BIST) modules enabling stimulus generation and measurements to be performed in the device itself. Typically, once development and testing of the device are complete, a physical or logic test fuse is blown. Blowing the fuse switches the device irreversibly from the test mode to a secure mode, where the TCU TAP can no longer be used, for example for unauthorized access to data stored in the device, and enables parts to be delivered safely to users.
Debugging of processors is typically performed after packaging. The debugging process may include detecting anomalies (such as logical or synchronization problems in the software code, or a design error in the hardware), diagnosing their cause (including running a program step by step, breaking the program at a particular event or specified instruction, and tracking the values of variables, for example), assessing their impact, and implementing software patches updating or adding software modules to a system. The DAP TAP in the device typically includes hardware and software elements for communicating with a debugger and executing the processes defined by the debugger. A packaged processor typically includes a few pins that are specific to the DAP TAP, commonly between two and five pins, in addition to the power supply and input/output (I/O) pins of the device for its normal functional operation.
One common tool for debug access to packaged devices is the Joint Test Action Group (JTAG), IEEE standard 1149.1. JTAG is a basic means of accessing sub-blocks of the device. A DAP TAP in a JTAG capable device may include a JTAG adapter module or in-circuit emulator (ICE) to access on-chip debug modules inside the processor through a user interface (UI) on a terminal. Another tool for debug access to packaged devices is the Background Debug Mode (BDM).
JTAG can also be used during testing to manipulate the boundary scan links in the device through its I/O pins, to manipulate interfaces in the device to internal registers and test the combinational logic of the device, and to activate BIST modules in the device.
Development of processors can be prolonged and even sequencing and programming an algorithm for blowing a test fuse may cause significant additional delay. It would be desirable to be able to supply a limited quantity of engineering samples for software development, evaluation and validation before the test fuse is blown. Such engineering samples should restrict access by users in the debug mode to the DAP TAP, the TCU TAP being only accessible to the TCU for the test mode, while still allowing the ATE to select access through either the TCU TAP or the DAP TAP.